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Senior SoC Validation Engineer

Senior SoC Validation Engineer
Full-time, on-site position in San Jose, CA
Range: 180-220k Base ++

A leading ASIC supplier of PCIe/CXL switches is seeking a highly motivated and experienced Senior SoC Post-Silicon Validation Engineer to validate PCIe and CXL switch functions at both chip and application levels.
 
Job Description: The SoC Validation Engineer will leverage silicon evaluation platforms, software, and test equipment to validate functionality and design robustness before production. This role involves close collaboration with design teams to verify, stress-test, and ensure product compliance with specifications.


Responsibilities:

• Develop test plans based on PCIe and CXL specifications, aligning with architectural requirements and customer use cases.
• Define test methodologies and implement validation and testing standards.
• Perform feature and performance validation through scripting, regression testing, debugging, and analysis.
• Conduct compliance testing for high-speed serial interfaces, including PCIe Gen1-6, and perform lab measurements under PVT conditions.
• Work with hardware lab equipment such as oscilloscopes, BERT, protocol analyzers, and logic analyzers.
• Document technical findings and maintain detailed validation reports.
• Collaborate across teams, including board design, software, architecture, operations, and ATE.
• Mentor junior engineers, providing guidance and technical training.
• Communicate effectively and contribute to a diverse and inclusive engineering team.

 
Basic Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5-10+ years of experience in SoC/ASIC/FPGA validation.
• Strong hands-on experience with hardware lab equipment for high-speed serial interface validation.
• In-depth understanding of PCIe and CXL protocols, analog building blocks, and compliance testing.

 
Preferred Qualifications:

• Experience testing PCIe and CXL functionalities.
• Proficiency in Python, C++, or other scripting languages for test automation.
• Experience in SerDes, PLL, DDR characterization is a plus.

 
 
This role offers an opportunity to work on cutting-edge computing platforms for AI and data center applications, contributing to the validation of next-generation PCIe/CXL switch ASICs.
 

Note: Any pay ranges displayed are estimations.  Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description.  All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit  https://www.yoh.com/applicants-with-disabilities  to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act.  All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.