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DFT/DFD Verification Engineer – Advanced SoC Projects

DFT/DFD Verification Engineer – Advanced SoC Projects
We are looking for a seasoned Design-for-Test / Design-for-Debug Verification Engineer focused on validating sophisticated test and debug logic within next-generation SoCs. This position involves verifying scan architectures—such as JTAG, iJTAG, and other internal debug features—to support robust manufacturing testability and effective post-silicon debugging. The role will require tight collaboration with engineering teams across design, integration, and verification to deliver on coverage and quality goals using modern simulation and debug tools.
This contract opportunity is open to candidates located in the U.S. or Canada, with the option to work remotely.

Scope:
• Define and carry out verification strategies for scan and debug components (e.g., boundary scan, scan chains, JTAG logic)
• Write directed and UVM-based tests for validating compliance with IEEE 1149.1, 1500, and 1687 specifications
• Validate integration and runtime behavior of ICL and PDL content for instrument control and scan configuration
• Execute RTL and gate-level simulations using established EDA tools; identify and resolve functional or timing issues
• Collaborate with architects and implementation teams to ensure design intent aligns with test coverage and manufacturing objectives
• Drive both functional and code coverage targets to closure for all DFT/DFD modules
• Work with silicon validation and ATE engineering groups to ensure simulation and physical test data alignment

Required:
• Degree (B.S./M.S.) in Electrical or Computer Engineering or a closely related discipline
• Prior experience in SoC-level DFT/DFD design verification workflows
• Working knowledge of IEEE 1149.x, 1500, and 1687 standards
• Hands-on expertise developing and debugging ICL/PDL artifacts for pattern generation and debug instrumentation
• Familiarity with scan tool flows like Siemens Tessent or equivalent
• Proficient in Verilog/SystemVerilog and scripting (Python, Perl, TCL)
• Strong skills in debugging simulation output and documenting results clearly

Pluses:
• Use of UVM-based verification environments for DFT/DFD
• Experience with scan compression, MBIST/LBIST, and other test access methodologies
• Exposure to gate-level sim workflows and post-silicon test correlation
• Understanding of scan diagnostics and failure analysis techniques
• Experience collaborating across design, ATE, and validation teams in a fast-paced silicon environment


Estimated Min Rate: $50.00
Estimated Max Rate: $80.00


What’s In It for You?
We welcome you to be a part of the largest and legendary global staffing companies to meet your career aspirations. Yoh’s network of client companies has been employing professionals like you for over 65 years in the U.S., UK and Canada. Join Yoh’s extensive talent community that will provide you with access to Yoh’s vast network of opportunities and gain access to this exclusive opportunity available to you. Benefit eligibility is in accordance with applicable laws and client requirements. Benefits include:

• Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
• Health Savings Account (HSA) (for employees working 20+ hours per week)
• Life & Disability Insurance (for employees working 20+ hours per week)
• MetLife Voluntary Benefits
• Employee Assistance Program (EAP)
• 401K Retirement Savings Plan
• Direct Deposit & weekly epayroll
• Referral Bonus Programs
• Certification and training opportunities

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.